1. Field of the Invention
The present invention relates to a memory and method of manufacturing the same, more particularly, to a ferroelectric memory and a method of making the same.
2. Discussion of the Related Art
Ferroelectric random access memory (FRAM) having data processing speed as fast as DRAM, which is generally used as semiconductor memories and keeping the stored data when a supplied power is off, is getting attention in the memory of next generation. The FRAM is a memory device having almost the same structure as the DRAM but the data stored in the memory is not lost when electric field is lost from the memory because a ferroelectric having a characteristic of a high residual polarization is used as the material of its capacitor.
In other words, as shown in the hysteresis loop of FIG. 1, a polarization induced by an electric field is not vanished because of the existence of its spontaneous polarization even though the electric field is removed but maintains a constant state (d and a states). This device is used as a memory by corresponding the d and a states to 1 and 0, respectively. Such device is described in U.S. Pat. No. 4,873,644 to Eaton, Jr.
FIG. 2 is circuitry of a background art ferroelectric memory, and FIG. 3 is a timing waveform to explain the operation of the background art ferroelectric memory. An ideal structure of FRAM having a ferroelectric thin film is provided with one transistor and one capacitor (1T/1C) which is similar to DRAM, but it has a serious problem in providing a high degree of integration which is difficult to be solved if new electrode and barrier materials are not invented. The problem in the high degree of integration is that the capacitor cannot be directly formed on a silicon substrate or on a polysilicon, and therefore the size of the memory is larger than the DRAM of the same size. Furthermore, if the electric field is repeatedly applied to the ferroelectric, a fatigue phenomenon having a gradually decreased residual polarization occurs and a problem of reliability of the memory remains.
In order to replace the FRAM having such problems, FRAM of 2T/2C (two transistors and two capacitors) shown in FIG. 2 is suggested under consideration of all practical matters (substitute electrode material, integration, stability of an ferroelectric thin film, reliability of operation, etc.). The FRAM of 2T/2C is provided with first and second transistors (T1, T2) 1 and 3 whose gates are commonly connected to a word line 5 and first and second ferroelectric capacitors (C1, C2) 2 and 4. A drain and a source of the first transistor 1 are connected to a bit line 6 and a node (N1), respectively, and a drain and a source of the second transistor 3 are connected to a /bit line 7 and a node (N2), respectively. The first ferroelectric capacitor 2 is connected between the node (N1) and a cell plate line (CPL) 8, and the second ferroelectric capacitor 4 is connected between the node (N2) and the cell plate line (CPL) 8.
The operation of the 2T/2C FRAM is explained hereafter. As shown in the timing waveform of FIG. 3, if a signal applied to the word line 5 in the time interval T1 is enabled from low to high, all selected cells are conducted between the bit line 6 and the /bit line 7. In this state, if a signal applied to the word line 5 is enabled from low to high, the memory cell data is transferred to the bit line 6 and the /bit line 7. A sense amplifier senses the signal, amplifies it and then feeds the amplified signal back to the bit line 6 and /bit line 7. If it is required that the destroyed data of the first and second ferroelectric capacitors 2 and 4 are recovered, the potential of the word line 5 is kept a high state and the potential of cell plate line 8 is disabled from a high state to a low state. Then, the destroyed data are restored.
The structure of the background art 2T/2C FRAM and its manufacturing method are explained in the following. FIG. 4 is a cross sectional view of a background art ferroelectric memory, and FIGS. 5a to 5i are the cross sectional views of the manufacturing process of the background art ferroelectric memory. This background art FRAM is provided with a gate electrode 42 formed on a semiconductor substrate 41, source/drain regions 43 formed in the semiconductor substrate 41 on both sides of the gate electrode 42. A lower electrode layer 44 is in contact with one of the source/drain regions; a ferroelectric layer 45 is formed on the lower electrode layer 44 of the capacitor; and an upper electrode layer 46 of the capacitor is formed on said ferroelectric layer 45. The bit line and /bit line 47 is in contact with the other source/drain regions 43, and a cell plate line 48 is in contact with the upper electrode layer 46 of the capacitor. First, second and third insulation layers 49, 50, and 51 are formed for isolation.
The manufacturing process for the background art ferroelectric memory is as follows. As shown in FIG. 5a, a field oxide layer 51 formed in the element isolation region of the semiconductor substrate 50 defines as an active region in which the first and second transistors 1 and 3 are to be formed. Referring to FIG. 5b, a gate line 53 of each of the first and second transistors is formed in the active region 52 defined by the field oxide layer 51 of each transistor.
Referring to FIG. 5c, by an impurity ion injection process using the gate line 53 as a mask, the source/drain 54 of the first and second transistors 1 and 3 is formed. Referring to FIG. 5d, a first insulation layer 55 is formed on the whole surface, and a first insulation layer 55 on one of source/drain region 54 of the first and second transistors 1 and 3 is selectively removed where the first contact hole 56 is to be formed. Referring to FIG. 5e, a lower electrode material layer 57 is formed so that the first contact hole 56 is buried, and on the lower electrode material layer 57, a ferroelectric layer 58 and an upper electrode material layer 59 are formed in sequence. The upper electrode material layer 59, ferroelectric layer 58 and lower electrode material layer 57 are selectively etched and therein the first and second ferroelectric capacitors 2 and 4 are formed.
Referring to FIG. 5f, a second insulation layer 60 is formed on the surface of the semiconductor substrate 50 on which the first and second ferroelectric capacitors 2 and 4 are formed. The second insulation layer 60 on the other side of the source/drain region 54 of the first and second transistors 1 and 3 is selectively removed, and thereat, a second contact hole 61 is formed. Referring to FIG. 5g, by completely burying the second contact hole 61, the bit line and /bit line 62, which are in contact with the other source/drain region 54 of the first and second transistors 1 and 3, are formed.
Referring to FIG. 5h, a third insulation layer 63 is formed on the surface on which the bit line and /bit line 62 are formed. The second insulation layer 60 and the third insulation layer 63 on the upper side of the ferroelectric capacitor are selectively removed and thereat a third contact hole 64 is formed. A third contact hole 64, which is to connect the upper electrode material layer 59 of the capacitor with a cell plate line which is to be formed. Referring to FIG. 5i, a cell plate line 65 is formed so that the line is in contact with the upper electrode material layer 59 and the third contact hole 65 is completely filled up. Thus, the background art 2T/2C FRAM has a speed as high as DRAM but keeps the stored data even when the power is lost.
Although the background art FRAM has a merit of keeping the stored data when the power is lost, the layout of the background art FRAM is difficult because of its separate cell plate line, and therefore the manufacturing process is complicated and the cost increases greatly. Furthermore, the control for a read or write mode operation is also difficult, and therefore, the efficiency as a memory is decreased.